The present integrated circuit devices comprise a silicon substrate, doped regions in the semiconductor to which source or drain connections are made, separated by a gate control region. Metal connections to the source, gate, and drain electrodes are made by multilayer interconnects, which are supported over the substrate by an interlayer dielectric. To make electrical connection between different layers, the dielectric is sequentially patterned and etched to form contact openings. These opening are filled with plugs of an electrically conductive material such as aluminum. Some plugs contact a polysilicon layer which is formed over a thin oxide gate layer and these plugs become gate electrodes. Other plugs contact previously-doped regions in the semiconductor substrate and become source or drain contacts.
In the case where source and drain contacts are to be made, a titanium silicide layer is formed on the doped regions by use of a rapid thermal anneal. To support multilayer interconnects, an interlayer dielectric comprising of oxide is deposited on the surface and contact openings are etched in the interlayer dielectric.
The current practice in the industry is to deposit a Ti/TiN layer onto the titanium silicide layer after the contact openings are formed. The Ti/TiN layer serves as a barrier TiN layer that protects the junctions below. The formation of a barrier TiN layer is needed to prevent junction spiking caused by diffusion of metal from the plugs into the junctions. The minimum thickness of the barrier TiN layer depends on the device. Presently, physical vapor deposition (PVD) or chemical vapor deposition (CVD) is employed to deposit the barrier TiN layer.
What is needed is an improved process for forming a barrier TiN layer at the bottom of the contact opening.